Decoding method, decoding device, program, recording/reproduction device and method, and reproduction device and method

ABSTRACT

The present invention relates to a decoding method and a decoder, a program, a recording-and-reproducing apparatus and a method, and a reproducing apparatus and a method that are suitable for decoding encoded data encoded by using a linear code on ring R. A low-density processing unit performs parity-check-matrix low-density processing, performs linear combination for rows of a parity check matrix included in an obtained reception word, and generates a parity check matrix according to the linear-combination result, thereby reducing the density of the parity check matrix used for decoding, at step S 21.  Then, at step S 22,  an LDPC decoding unit performs decoding by using a sum product algorithm (SPA) by using the parity check matrix whose density is reduced through the processing performed at step S 21.  Where the processing at step S 22  is finished, the LDPC decoding unit finishes decoding for the reception word. The present invention can be used for an error-correction system.

TECHNICAL FIELD

The present invention relates to a decoding method and a decoder, aprogram, a recording-and-reproducing apparatus and a method, and areproducing apparatus and a method, and particularly relates to adecoding method and a decoder, a program, a recording-and-reproducingapparatus and a method, and a reproducing apparatus and a method thatare suitable for decoding encoded data encoded by using a linear code onring R.

BACKGROUND ART

In recent years, as the field of communications such as mobilecommunications and deep-space communications, and the field of broadcastsuch as ground-wave broadcast and satellite digital broadcast arestudied with remarkable progress, for example, the coding theory isactively studied to increase the efficiency of error-correction encodingand decoding.

Shannon limit presented by so-called Shannon (C. E. Shannon)communication-path encoding theorem is known, as the theoretical limitsof code performance. The coding theory is studied for developing a codethat presents performance approaching the above-described Shannon limit.In recent years, a method referred to as so-called turbo codingincluding parallel concatenated convolutional codes (PCCC), seriallyconcatenated convolutional codes (SCCC), and so forth, was developed, asan encoding method that presents performance approaching Shannon limit.Further, aside from the turbo codes being developed, a known encodingmethod, that is, low-density parity check codes (hereinafter referred toas LDPC codes) are receiving attention.

The LDPC code was suggested first time in “R. G. Gallager, “Low DensityParity Check Codes”, Cambridge, Mass.: M.I.T.Press, 1963” by R. G.Gallager. Then, the LDPC code receives further attention by “D. J. C.MacKay, “Good error correcting codes based on very sparse matrices”,Submitted to IEEE Trans. Inf. Theory, IT-45, pp. 399-431, 1999, “M. G.Luby M. Mitzenmacher, M. A. Shokrollahi and D. A. Spielman, “Analysis oflow density codes and improved designs using irregular graphs”, inProceedings of ACM Symposium on Theory of Computing, pp. 249-258, 1998”,and so forth.

According to studies in recent years, the performance of the LDPC codeapproaches Shannon limit with increases in the code length. Further,since the minimum distance of the LDPC code is proportional to the codelength, the LDPC code has the following advantages, as its features.That is to say, the LDPC code has high block-error probability qualitiesand hardly causes a so-called error-floor phenomenon that is observed inqualities of decoding turbo codes or the like.

The above-described LDPC code will be described in detail, as below. TheLDPC code is a linear code and not necessarily binary. However, in thisspecification, it will be described on the assumption that the LDPC codeis binary.

The major characteristic of the LDPC code is that a parity check matrixdefining the LDPC code is sparse. Here, the sparse matrix denotes amatrix including very few components whose values are “1”. The sparsecheck matrix is designated by reference character H. The sparse checkmatrix includes H_(LDPC) shown in FIG. 1, where Hamming weight (thenumber of “1”) of each row is “2” and that of each column is “4”, forexample.

Thus, the LDPC code defined by a check matrix H, where Hamming weight ofeach of the rows and columns is constant, is referred to as a regularLDPC code. On the other hand, an LDPC code defined by a check matrix H,where Hamming weight of each of the rows and columns is not constant, isreferred to as an irregular LDPC code.

Encoding by using the above-described LDPC code is achieved by agenerating generation matrix G based on the check matrix H andgenerating a code word by multiplying the generation matrix G bybinary-data message. More specifically, first, an encoder for performingencoding by the LDPC code calculates the generation matrix G, where anequation GH^(T)=0 holds, between the check matrix H and a transposedmatrix H^(T). Where the generation matrix G is a k×n matrix, the encodermultiplies the generation matrix G by a k-bit data message (vector u)and generates an n-bit code word c (=uG). In the code word generated bythe encoder, a code bit whose value is “0” is mapped to “+1” and a codebit whose value is “1” is mapped to “1”. Then, the code word istransmitted and received on the reception side via a predeterminedcommunication path.

Decoding of the LDPC code can be performed by using an algorithm namedand proposed by Gallager, as probabilistic decoding, that is, a messagepassing algorithm by belief propagation on a so-called Tanner graphincluding a variable node (sometimes referred to as a message node) anda check node. Hereinafter, the variable node and the check node aresimply referred to as nodes, as required.

For example, the parity check matrix HLDC shown in FIG. 1 is expressedby a Tanner graph shown in FIG. 2. In the Tanner graph shown in FIG. 2,each column of the parity check matrix H_(LDPC) shown in FIG. 1 isdetermined to be a variable node and each row is determined to be acheck node. Further, the j-th variable node and the i-th check node areconnected to an element whose value is “1” on the i-th row and the j-thcolumn of the parity check matrix H_(LDPC), as edges.

However, where the probability decoding is performed, the value of amessage transmitted between the nodes is given, as a real number.Subsequently, there is a need to track the probability distribution ofmessages having consecutive values for analytical solution, which isextremely difficult. Therefore, Gallager proposed algorithms A and B, asan algorithm for decoding the LDPC code.

Usually, the LDPC-code decoding is achieved by performing proceduresshown in FIG. 2. Here, in this case, a reception value (a received codesequence) is determined to be U₀(u_(0i)), a message transmitted from thecheck node is determined to be u_(j), and a message transmitted from thevariable node is determined to be vi. Further, in this case, the messageis a real-number value indicating the probability that the value is “0”,as a so-called log likelihood ratio.

Usually, decoding the LDPC code is achieved by performing proceduresshown in FIG. 3. Here, in this case, the reception value (the receivedcode sequence) is determined to be U₀(u_(0i)), the message transmittedfrom the check node is determined to be u_(j), and the messagetransmitted from the variable node is determined to be v_(i). Further,in this case, the message is the real-number value indicating theprobability that the value is “0”, as the so-called log likelihoodratio.

First, for decoding the LDPC code, a reception value U₀(u_(0i)) isreceived, a message u_(j) is initialized to “0”, and a variable k thatis an integer functioning as a counter of repetition processing isinitialized to “0”, at step S1, and the processing advances to step S2,as shown in FIG. 3. At step S2, the message v_(i) is obtained byperforming calculation shown by Equation (1) (variable-node calculation)based on the reception value U₀(u_(0i)), and the message u_(j) isobtained by performing calculation shown in Equation (2) (check-nodecalculation) based on the message v_(i). $\begin{matrix}{v_{i} = {u_{0i} + {\sum\limits_{j = 1}^{d_{v} - 1}u_{j}}}} & {{Equation}\quad(1)} \\{{\tanh\left( \frac{u_{j}}{2} \right)} = {\prod\limits_{i = 1}^{d_{c} - 1}{\tanh\left( \frac{v_{i}}{2} \right)}}} & {{Equation}\quad(2)}\end{matrix}$

Here, d_(v) and d_(c) shown in Equations (1) and (2) are parameters thatindicate the number of “1” along the vertical direction (columns) andthe horizontal direction (rows) of the check matrix H and that can bearbitrarily selected, respectively. For example, in the case of a code(3, 6), equations d_(v)=3 and d_(c)=6 hold.

Further, in the calculations shown by Equations (1) and (2), a messageinput from an edge for outputting messages (a line connecting thevariable node to the check node) is not used, as a parameter of sumoperation or product operation. Therefore, the area of sum or productoperation is determined to be 1 to d_(v)−1, or 1 to d_(c)−1. Further,the calculation shown in Equation (2) is actually performed bygenerating a table of a function R(v₁, v₂) shown in Equation (3) definedby one output for two inputs v1 and v2 in advance, and using the tableconsecutively (recursively), as shown in Equation (4).x=2tan h ⁻¹{tan h(v₁/2)tan h(v₂/2)}=R(v ₁ , v ₂)   Equation (3)u _(j) =R(v ₁ , R(v ₂ , R(v ₃ , . . . , R(v _(d) _(c) ⁻² , v _(d) _(c)⁻¹⁾⁾⁾⁾   Equation (4)

At step S2, further, the variable k is incremented by “1”, and theprocessing advances to step S3. At step S3, it is determined whether ornot the variable k is larger than a predetermined repetition-decodingnumber N. Where it is determined that the variable k is not larger thanN, at step S3, the processing returns to step S2, and the sameprocessing is repeated thereafter.

Further, where it is determined that the variable k is larger than N, atstep S3, the processing advances to step S4, so that the calculationshown in Equation (5) is performed, whereby the message v_(i) isobtained and output, as a decoding result that is finally output. Then,the LDPC-code decoding is finished. $\begin{matrix}{v_{i} = {u_{0i} + {\sum\limits_{j = 1}^{d_{v}}u_{j}}}} & {{Equation}\quad(5)}\end{matrix}$

Here, different from the calculation shown in Equation (1), thecalculation shown in Equation (5) is performed by using messages inputfrom all the edges connected to the variable node.

Where the LDPC-code decoding is performed by using the code (3, 6), forexample, messages are transmitted between the nodes, as shown in FIG. 4.Further, the calculation shown in Equation (1) is performed at nodesindicated by signs “=” (variable nodes) shown in FIG. 4 and thecalculation shown in Equation (2) is performed at nodes indicated bysigns “+” (check nodes). Particularly, in the case of an algorithm A,the messages are divided into two and an exclusive OR operation isperformed for d_(c)−1 input messages at the nodes indicated by the signs“+”. Where all the bit values of d_(v)−1 input messages are differentfrom one another for a reception value R at the nodes indicated by thesigns “=”, the code is reversed and output.

Aside from the above-described technology, in recent years, methods formounting the LDPC-code decoding are studied. First, the LDPC-codedecoding will be schematically described before describing the mouthingmethod.

FIG. 5 is an example parity check matrix of the LDPC code (3, 6) (wherethe encoding ratio is ½ and the code length is 12). The parity checkmatrix of the LDPC code can be written through a Tanner graph, as shownin FIG. 6. Here, in FIG. 6, check nodes are indicated by signs “+” andvariable nodes are indicated by signs “=”. The check nodes and thevariable nodes correspond to the rows and columns of the parity checkmatrix, respectively. Connections between the check nodes and thevariable nodes are edges and correspond to “1” of the parity checkmatrix. That is to say, where a component in the j-th row and the i-thcolumn of the parity check matrix is one, the i-th variable node (a nodeindicated by the sign “=”) from top and the j-th check node (a nodeindicated by the sign “+”) from top are connected to each other by theedge, as shown in FIG. 6. The edge indicates that a code bitcorresponding to the variable node has a constraint conditioncorresponding to the check node. Further, FIG. 6 shows the Tanner graphof the parity check matrix shown in FIG. 5.

A sum product algorithm can be used, as the LDPC-code decoding method(Refer to “Tadashi Wadayama, “Low density parity check code andsum-product algorithm”, [online], Jun. 22, 2001, Okayama PrefecturalUniversity, [searched on May 19, 2003], the Internet<URL:http://vega.c.oka-pu.ac.jp/-wadayama/pdf/LDPC.pdf>”, for example.).

According to the sum product algorithm, the variable-node operation andthe check-node operation are performed repetitively.

At the variable node, the operation shown in Equation (1) (thevariable-node operation) is performed, as shown in FIG. 7. That is tosay, according to FIG. 7, the message v_(i) corresponding to an edge forwhich a calculation is to be performed is calculated by using messagesu₁ and u₂ transmitted from the other edges connected to the variablenode and the reception data u_(0i). Messages corresponding to the otheredges are calculated in the same manner.

Next, Equation (2) is rewritten by using the relation expressed by theequation a×b=exp{ln(|a|)+ln(|b|)}×sign(a)×sign(b), as shown by Equation(6), before describing the check-node operation. Here, where theexpression x≧0 holds, the sign(x) is one, and where the expression x<0holds, the sign(x) is negative one. $\begin{matrix}\begin{matrix}{u_{j} = {2{\tanh^{- 1}\left( {\prod\limits_{i = 1}^{d_{c} - 1}{\tanh\left( \frac{v_{i}}{2} \right)}} \right)}}} \\{= {2{\tanh^{- 1}\left\lbrack {\exp\left\{ {\sum\limits_{i = 1}^{d_{c} - 1}{\ln\left( {{\tanh\left( \frac{v_{i}}{2} \right)}} \right)}} \right\} \times} \right.}}} \\\left. {\prod\limits_{i = 1}^{d_{c} - 1}{{sign}\left( {\tanh\left( \frac{v_{i}}{2} \right)} \right)}} \right\rbrack \\{= {2{\tanh^{- 1}\left\lbrack {\exp\left\{ {- \left( {\sum\limits_{i = 1}^{d_{c} - 1}{- {\ln\left( {\tanh\left( \frac{v_{i}}{2} \right)} \right)}}} \right)} \right\}} \right\rbrack} \times}} \\{\prod\limits_{i = 1}^{d_{c} - 1}{{sign}\left( v_{i} \right)}}\end{matrix} & {{Equation}\quad(6)}\end{matrix}$

Further, where the expression x≧0 holds and φ(x) is defined as ln(tanh(x/2)), the expression φ⁻¹(x)=2 tan h⁻¹(e^(−x)) holds. Therefore,Equations (6) can be written, as shown by Equation (7). $\begin{matrix}{u_{j} = {{\phi^{- 1}\left( {\sum\limits_{i = 1}^{d_{c} - 1}{\phi\left( {v_{i}} \right)}} \right)} \times {\prod\limits_{i = 1}^{d_{c} - 1}{{sign}\left( v_{i} \right)}}}} & {{Equation}\quad(7)}\end{matrix}$

The operation shown in Equation (7) (check-node operation) is performed,at the check node, as shown in FIG. 8. That is to say, in FIG. 8, themessage u_(j) corresponding to an edge for which a calculation is to beperformed is calculated by using messages v₁, v₂, v₃, v₄, and v₅transmitted from the other edges connected to the check node. Messagescorresponding to the other edges are calculated in the same manner.

Further, the function φ(x) can be expressed, as the equationφ(x)=ln((e^(x)+1)/(e^(x)−1)). Further, the function φ(x) can beexpressed, as the equation φ(x)=φ⁻¹(x), where the expression x>0 holds.The functions φ(x) and φ⁻¹(x) are often mounted on hardware by using anLUT (look up table). The same LUT can be used for both the functions.

Where the sum product algorithm is mounted on hardware, thevariable-node operation shown in Equation (1) and the check-nodeoperation shown in Equation (7) need to be performed repetitively byusing a circuit with suitable size and at suitable operationfrequencies.

Further, methods for calculating the cost of LDPC-code operation usingthe above-described sum product algorithm are widely known (Refer to“Matthew C. Davey, David J C MacKay “Low Density Parity Check Codes overGF(q)””, for example.).

For obtaining high decoding qualities by using the sum product algorithm(SPA) as described above, the density of the parity check matrix must below.

Further, FIG. 9 shows a parity check matrix H of the other ordinarylinear code, such as a Reed-Solomon code, where the primitive root of adefinition field is determined to be a. Usually, the density of theparity check matrix H of a linear code is not low, as shown in FIG. 9.For the Reed-Solomon code whose density is not low, decoding usingEuclid's algorithm or the like (hereinafter referred togas ordinarydecoding) is performed.

FIG. 10 is a block diagram illustrating the configuration of an exampleerror-correction system for performing error correction by using theReed-Solomon code. The error-correction system shown in FIG. 10 is asystem used for a digital-communication system such as a digital TV, forexample.

In the error-correction system shown in FIG. 10, digital datatransmitted from an encoder 10 on the transmission side is transmittedto a decoder 30 on the reception side via a communication path 21 suchas the Internet, for example.

The encoder 10 includes a Reed-Solomon encoding unit 11 for encodingexternally transmitted digital data for transmission by using theReed-Solomon code, an interleaver 12 for rearranging the encoded digitaldata, a convolutional-encoding unit 13 for performing convolutionalencoding, and a communication processing unit 14 for communicating withthe decoder 30 via the communication path 21.

Further, the decoder 30 includes a communication processing unit 31 forobtaining a transmission word transmitted via the communication path 21,a convolutional-decoding unit 32 for performing convolutional decodingfor the obtained transmission word, a deinterleaver 33 for resetting therearranged data to the original order, and a Reed-Solomon decoding unit34 for performing Reed-Solomon decoding (ordinary decoding).

The transmission digital data transmitted from outside the encoder 10 isencoded into a Reed-Solomon code through the Reed-Solomon encoding unit11 of the encoder 10 and transmitted to the interleaver 12. Theinterleaver 12 performs data rearranging (interleaving) for diffusingburst errors that occur mainly in the communication path 21. Since theReed-Solomon code performs error correction, where a plurality of bitsis regarded as a single symbol, the interleaver 12 performs symbolinterleaving for diffusing the burst errors per symbol.

The rearranged transmission digital data is further subjected toconvolutional encoding through the convolutional-encoding unit 13 basedon a plurality of data blocks so that code sequences are determined insequence. For example, upon receiving the digital data for each k-bitdata block from the interleaver 12, the convolutional-encoding unit 13with a constraint length K encodes the digital data to an n-bit codeblock based on not only the data block transmitted at that time but alsoK data blocks including data blocks that had been provided.

Then, the convolutional-encoded digital data is converted to data thatcan be transmitted through the communication processing unit 14 andtransmitted to the decoder 30 via the communication path 21.

The decoder 30 obtains the transmission word transmitted via thecommunication path 21 wired or unwired in the communication processingunit 31. The obtained transmission word is subjected to convolutionaldecoding through the convolutional-decoding unit 32. Upon receiving theconvolutional-decoded data, the deinterleaver 33 performs processing forresetting the rearranged data to the original order (deinterleaving)through rearranging the data according to a method corresponding to theinterleaving performed by the interleaver 12 of the encoder. TheReed-Solomon decoding unit 34 performs Reed-Solomon decoding by ordinarydecoding for the digital data reset to the original order, reconstitutesthe digital data in the previous state where Reed-Solomon encoding isnot yet performed, and transmits the data to outside the decoder 30.

In the above-described manner, the error correction system shown in FIG.10 corrects errors occur during communications and performscommunications more precisely than ever.

FIG. 11 is a block diagram illustrating the configuration of an examplerecording-and-reproducing apparatus using the error correction systemfor performing the error correction by using the Reed-Solomon code. Therecording-and-reproducing apparatus shown in FIG. 11 is adigital-recording-medium recording-and-reproducing apparatus such as aDVD (Digital Versatile Disc) record player, for example.

The recording-and-reproducing apparatus 50 shown in FIG. 11 encodes theexternally transmitted digital data through the encode-processing unit60 and records the digital data onto a recording medium 72 in arecording-and-reproducing unit 70. Further, therecording-and-reproducing apparatus 50 reproduces the digital datarecorded on the recording medium 72 in the recording-and-reproducingunit 70, obtains the original digital data through performing decodingin a decoding unit 80, and externally outputs the data.

The encode-processing unit 60 includes first to n-th Reed-Solomonencoding units 61-1 to 61-n for performing Reed-Solomon encoding for thedigital data, where the Reed-Solomon encoding relates to degrees thatare different from one another.

The recording-and-reproducing unit 70 includes a recording unit 71 forrecording the data transmitted from the encode-processing unit 60 ontothe recording medium 72, the recording medium 72 such as an opticaldisk, for example, and a reproducing unit 73 for reproducing the datarecorded on the recording medium 72.

Further, the decode-processing unit 80 is a decoder corresponding to theencode-processing unit 60 and includes first to n-th Reed-Solomondecoding units 81-1 to 81-n for performing Reed-Solomon decoding(ordinary decoding) relating to degrees that are different to oneanother for the digital data.

The digital data transmitted from outside the encode-processing unit 60is subjected to Reed-Solomon encoding relating to degree one in thefirst Reed-Solomon encoding unit 61-1. Then, the digital data issequentially subjected to Reed-Solomon encoding relating to each ofdegrees two to n in the second to n-th Reed-Solomon encoding units 61-2to 61-n. Where the n-th Reed-Solomon encoding unit 61-n finishesencoding, the encode-processing unit 60 transmits the encoded digitaldata to the recording-and-reproducing unit 70. The recording unit 71 ofthe recording-and-reproducing unit 70 records the digital datatransmitted from the encode-processing unit 60 onto the recording medium72.

The reproducing unit 73 of the recording-and-reproducing unit 70reproduces the digital data recorded on the recording medium 72 (theencoded digital data) and transmits the digital data to thedecode-processing unit 80.

The decode-processing unit 80 performs Reed-Solomon decoding (ordinarydecoding) relating to each degree for the digital data transmitted fromthe reproducing unit 73 in the first to n-th Reed-Solomon decoding units81-1 to 81-n and reconstitutes the original digital data. Further, thedecode-processing unit 80 performs decoding that is the reverse ofdecoding performed by the encode-processing unit 60. First, thedecode-processing unit 80 performs decoding relating to degree n in then-th Reed-Solomon decoding unit 81-n, and subsequently performs theReed-Solomon decoding in decreasing order of degrees, that is, fromdegree n-1 to degree n-2. Finally, the decode-processing unit 80performs decoding relating to the first degree. The decode-processingunit 80 outputs the reconstituted original digital data to outside therecording-and-reproducing apparatus 50.

As has been described, the recording-and-reproducing apparatus 50 shownin FIG. 11 corrects data errors that occur during data recording orreproducing.

The ordinary decoding for the above-described Reed-Solomon code, a BCH(Bose-Chaudhuri-Hocquenghem) code, and so forth, is a decoding methodused for a hard-decision reception word where a reception value isestimated to be only “0” or “1”.

However, where a soft-decision reception word is obtained and where aReed-Solomon code is subjected to the ordinary decoding in a system thatcan obtain the soft-decision reception word, the decoding quality islow. This is because the decoding quality obtained by using thehard-decision reception word is usually lower than in the case where thesoft-decision reception word is used.

Subsequently, the above-described method for decoding by using the sumproduct algorithm is considered. However, since the density of a paritycheck matrix of a widely-used linear code is not low in most cases, thedecoding quality does not increase. Further, if the density of aprovided parity check matrix was low, the configuration of a sum productalgorithm on a large finite field would be much complicated, which wouldincrease the operation cost.

DISCLOSURE OF INVENTION

Accordingly, the present invention is achieved for easily performinghigh-performance decoding in the case where a sum product algorithm isused, as a method for decoding an ordinary linear code.

A first decoding method of the present invention is characterized byincluding a low-density processing step for reducing the density ofelements whose values are determined to be one, for a check matrix ofthe linear code, and a decoding step for decoding the linear codethrough a sum product algorithm by using the check matrix whose densityis reduced through the low-density processing step.

The ring may be a finite field including powers of prime numbers, aselements.

The linear code may include a BCH code, or a Reed-Solomon code on thefinite field.

The low-density processing step may include a linear-combinationcalculation step for calculating linear combination of rows of the checkmatrix, and a check-matrix generation step for extracting a subset oflower-weight vectors for forming a complementary space from among avector set obtained by the linear combination calculated through thelinear-combination calculation step and generating a new check matrixincluding all the vectors of the vector subset, as row elements.

The low-density processing step may further include an expansion stepfor expanding the check matrix on the finite field on a predeterminedsubfield of the finite field in a predetermined degree. Thelinear-combination calculation step may be provided for calculatinglinear combination of the rows of the check matrix expanded through theexpansion step.

A first decoder of the present invention is characterized by includinglow-density processing means that performs low-density processing forreducing the density of elements whose values are determined to be one,for a check matrix of the linear code, and decoding means for decodingthe linear code through a sum product algorithm by using the checkmatrix whose density is reduced by the low-density processing means.

The ring may be a finite field including powers of prime numbers, aselements.

The linear code may include a BCH code, or a Reed-Solomon code on thefinite field.

The low-density processing means may include linear-combinationcalculation means for calculating linear combination of rows of thecheck matrix and check-matrix generation means for extracting a subsetof lower-weight vectors for forming a complementary space from among avector set obtained by the linear combination calculated by thelinear-combination calculation means and generating a new check matrixincluding all the vectors of the vector subset, as row elements.

The low-density processing means may further include expansion means forexpanding the check matrix on the finite field on a predeterminedsubfield of the finite field in a predetermined degree. Thelinear-combination calculation means may calculate linear combination ofrows of the check matrix expanded by the expansion means.

The decoder may further include soft-decision decoding means forperforming soft-decision decoding for a linear code subjected toconvolutional encoding. The low-density processing means reduces thedensity of the elements whose values are determined to be one, for thecheck matrix of the linear code subjected to the soft-decision decodingby the soft-decision decoding means.

The soft-decision decoding by the soft-decision decoding means, thelow-density processing by the low-density processing means, and thedecoding by the decoding means may be repetitively performed.

A first program of the present invention is characterized in that acomputer is made to perform a low-density processing step for reducingthe density of elements whose values are determined to be one, for acheck matrix of a linear code on ring R, and a decoding step fordecoding the linear code through a sum product algorithm by using thecheck matrix whose density is reduced through the low-density processingstep.

A second decoding method of the present invention is characterized byincluding an input step for inputting a reception value and a decodingstep for decoding a linear code through a sum product algorithm, for acheck matrix of the linear code, by using the check matrix, where thedensity of elements whose values are determined to be one is reduced,and the reception value input through the input step.

A second decoder of the present invention is characterized by includinginput means for inputting a reception value, and decoding means fordecoding a linear code through a sum product algorithm, for a checkmatrix of the linear code, by using the check matrix, where the densityof elements whose values are determined to be one is reduced, and thereception value input by the input means.

A second program of the present invention is characterized in that acomputer is made to perform an input step for inputting a receptionvalue and a decoding step for decoding a linear code through a sumproduct algorithm, for a check matrix of the linear code, by using thecheck matrix, where the density of elements whose values are determinedto be one is reduced, and the reception value input through the inputstep.

A first recording-and-reproducing apparatus of the present invention ischaracterized by including recording means for recording a linear codeon ring R onto a recording medium, reproducing means for reproducing thelinear code recorded by the recording means, low-density processingmeans that performs low-density processing for reducing the density ofelements whose values are determined to be one, for a check matrix ofthe linear code reproduced by the reproducing means, and decoding meansfor decoding the linear code through a sum product algorithm by usingthe check matrix whose density is reduced by the low-density processingmeans.

The linear code may be a linear code subjected to product coding in apredetermined degree, the low-density processing means may perform thelow-density processing for the check matrix for each degree, and thedecoding means may perform decoding through the sum product algorithmfor each degree of the low-density check matrix.

The low-density processing by the low-density processing means and thedecoding by the decoding means may be repetitively performed.

A first recording-and-reproducing method of the present invention ischaracterized by including a recording-control step for having controlover recording a linear code on ring R onto a recording medium, areproducing-control step for having control over reproducing the linearcode recorded under the control of the recording-control step, alow-density processing step for performing low-density processing forreducing the density of elements whose values are determined to be one,for a check matrix of the linear code reproduced under the control ofthe reproducing-control step, and a decoding step for decoding thelinear code through a sum product algorithm by using the check matrixwhose density is reduced through the low-density processing step.

A third program of the present invention is characterized in that acomputer is made to perform a recording-control step for having controlover recording a linear code on ring R onto the recording medium, areproducing-control step for having control over reproducing the linearcode recorded under the control of the recording-control step, alow-density processing step for performing low-density processing forreducing the density of elements whose values are determined to be one,for a check matrix of the linear code reproduced under the control ofthe reproducing-control step, and a decoding step for decoding thelinear code through a sum product algorithm by using the check matrixwhose density is reduced through the low-density processing step.

A second recording-and-reproducing apparatus of the present invention ischaracterized by including recording means for recording a linear codeon ring R onto the recording medium, reproducing means for reproducingthe linear code recorded by the recording means, decoding means fordecoding the linear code through a sum product algorithm, for a checkmatrix of the linear code, by using the check matrix, where the densityof elements whose values are determined to be one is reduced.

A second recording-and-reproducing method of the present invention ischaracterized by including a recording-control step for having controlover recording a linear code on ring R onto a recording medium, areproducing-control step for having control over reproducing the linearcode recorded under the control of the recording-control step, adecoding step for decoding the linear code through a sum productalgorithm, for a check matrix of the linear code, by using the checkmatrix, where the density of elements whose values are determined to beone is reduced.

A fourth program of the present invention is characterized in that acomputer is made to perform a recording-control step for having controlover recording a linear code on ring R onto the recording medium, areproducing-control step for having control over reproducing the linearcode recorded under the control of the recording-control step, and adecoding step for decoding the linear code through a sum productalgorithm, for a check matrix of the linear code, by using the checkmatrix, where the density of elements whose values are determined to beone is reduced.

A first reproducing apparatus of the present invention is characterizedby including reproducing means for reproducing a linear code on ring Rrecorded by recording means, low-density processing means for performinglow-density processing for reducing the density of elements whose valuesare determined to be one, for a check matrix of the linear codereproduced by the reproducing means, and decoding means for decoding thelinear code through a sum product algorithm by using the check matrixwhose density is reduced by the low-density processing means.

The linear code may be a linear code subjected to product coding in apredetermined degree and the low-density processing means may performthe low-density processing for the check matrix for each degree, and thedecoding means may perform decoding through the sum product algorithmfor each degree of the low-density check matrix.

The low-density processing by the low-density processing means and thedecoding by the decoding means may be repetitively performed.

A first reproducing method of the present invention is characterized byincluding a reproducing control step for controlling reproduction of alinear code on ring R recorded on the recording medium, a low-densityprocessing step for performing low-density processing for reducing thedensity of elements whose values are determined to be one, for a checkmatrix of the linear code reproduced under the control of thereproducing control step, and a decoding step for decoding the linearcode through a sum product algorithm by using the check matrix whosedensity is reduced through the low-density processing step.

A fifth program of the present invention is characterized in that acomputer is made to perform a reproducing control step for controllingreproduction of a linear code on ring R recorded on the recordingmedium, a low-density processing step for performing low-densityprocessing for reducing the density of elements whose values aredetermined to be one, for a check matrix of the linear code reproducedunder the control of the reproducing control step, and a decoding stepfor decoding the linear code through a sum product algorithm by usingthe check matrix whose density is reduced through the low-densityprocessing step.

A second reproducing apparatus of the present invention is characterizedby including reproducing means for reproducing a linear code on ring Rrecorded on a recording medium, and decoding means for decoding thelinear code through a sum product algorithm, for a check matrix of thelinear code, by using the check matrix, where the density of elementswhose values are determined to be one is reduced.

A second reproducing method of the present invention is characterized byincluding a reproducing control step for controlling reproduction of alinear code on ring R recorded on a recording medium and a decoding stepfor decoding the linear code through a sum product algorithm, for acheck matrix of the linear code, by using the check matrix, where thedensity of elements whose values are determined to be one is reduced.

A sixth program of the present invention is characterized in that acomputer is made to perform a reproducing control step for controllingreproduction of a linear code on ring R recorded on a recording mediumand a decoding step for decoding the linear code through a sum productalgorithm, for a check matrix of the linear code, by using the checkmatrix, where the density of elements whose values are determined to beone is reduced.

In the present invention, the density of elements whose values aredetermined to be one is reduced, for a check matrix of a linear code onring R, and the linear code is decoded by using a sum product algorithmby using the low-density check matrix.

Further, in the present invention, the linear code is decoded by usingthe sum product algorithm by using the check matrix, where the densityof elements whose values are determined to be one is reduced.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates an example low-density parity check matrix.

FIG. 2 illustrates a Tanner graph corresponding to the parity checkmatrix shown in FIG. 1.

FIG. 3 is a flowchart illustrating procedures for decoding an LDPC code.

FIG. 4 illustrates the flow of a message.

FIG. 5 illustrates an example check matrix of the LDPC code.

FIG. 6 illustrates a Tanner graph of the check matrix.

FIG. 7 shows a variable node.

FIG. 8 shows a check node.

FIG. 9 illustrates a check matrix of a Reed-Solomon code.

FIG. 10 illustrates the configuration of an example known errorcorrection system.

FIG. 11 illustrates the configuration of an example knownrecording-and-reproducing apparatus.

FIG. 12 illustrates the configuration of an example decoder using thepresent invention.

FIG. 13 is a flowchart illustrating decoding processing performed by thedecoder shown in FIG. 12.

FIG. 14 is a flowchart illustrating parity-check-matrix low-densityprocessing performed at step S21 shown in FIG. 13.

FIG. 15 illustrates an example parity check matrix of a BCH code.

FIG. 16 illustrates a Tanner graph corresponding to the parity checkmatrix shown in FIG. 15.

FIG. 17 illustrates an example expanded parity check matrix.

FIG. 18 illustrates a Tanner graph corresponding to the parity checkmatrix shown in FIG. 17.

FIG. 19 is a graph showing decoding comparisons.

FIG. 20 illustrates the configuration of another example decoder usingthe present invention.

FIG. 21 is a flowchart illustrating decoding processing performed by thedecoder shown in FIG. 20.

FIG. 22 illustrates an example parity check matrix of the Reed-Solomoncode.

FIG. 23 illustrates another example expanded parity check matrix.

FIG. 24 is another graph showing decoding comparisons.

FIG. 25 is a block diagram illustrating the configuration of an exampleerror correction system using the present invention.

FIG. 26 is a block diagram illustrating the configuration of anotherexample error correction system using the present invention.

FIG. 27 is a block diagram illustrating the configuration of an examplerecording-and-reproducing apparatus using the present invention.

FIG. 28 is a block diagram showing the configuration of an examplerecording apparatus.

FIG. 29 is a block diagram showing the configuration of an examplereproducing apparatus using the present invention.

FIG. 30 is a block diagram illustrating the configuration of anotherexample recording-and-reproducing apparatus using the present invention.

FIG. 31 is a block diagram showing the configuration of another examplereproducing apparatus using the present invention.

FIG. 32 is a block diagram illustrating the configuration of a computeraccording to an embodiment of the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiments of the present invention will be described, as below. First,an example technology using the present invention will be described.

FIG. 12 is a block diagram illustrating the example configuration of anexample decoder using the present invention.

In FIG. 12, a decoder 100 is a decoder that can be used for a BCH code,for example, and that includes a low-density processing unit 110 forconverting a parity check matrix of at least one reception word on ringR (or a finite field) into a matrix whose density is sufficiently lowand an LDPC decoding unit 121 for decoding the reception word by usingthe low-density parity check matrix.

The low-density processing unit 110 includes a linear-combinationcalculation unit 111 for calculating linear combination of rows of theparity check matrix, a parity-check-matrix generation unit 112 forgenerating a sufficiently sparse parity check matrix by using thelinearly combined rows, and a determination unit 113 for determiningwhether or not the rank of the generated parity check matrix is the sameas that of the original parity check matrix.

The linear-combination calculation unit 111 calculates the linearcombination of rows of a parity check matrix included in an obtainedreception word for all the combinations. That is to say, thelinear-combination calculation unit 111 calculates 2^(n)-ways of linearcombination for a parity check matrix having n rows. Thelinear-combination calculation unit 111 transmits the calculation resultand the reception words to the parity-check-matrix generation unit 112.

The parity-check-matrix generation unit 112 extracts rows from thecalculation result transmitted from the linear-combination calculationunit 111, that is, the linearly combined rows, from predeterminedcriteria, and generates a parity check matrix including the extractedrows. The parity-check-matrix generation unit 112 sets predeterminedcriteria so that the density of the generated parity check matrixbecomes low. For example, it may be arranged that a predetermined row isextracted from the linearly combined rows, where the number of elementswhose values are “1” is less than a predetermined number. Then, theparity-check-matrix generation unit 112 extracts at least one rowmeeting the criteria. The parity-check-matrix generation unit 112transmits the generated parity check matrix and the reception word tothe determination unit 113. Further, as will be described later, wherethe determination unit 113 determines that the rank of the generatedparity check matrix is different from that of the original parity checkmatrix, the parity-check-matrix generation unit 112 performs the rowextraction again, and generates a new parity check matrix. At that time,the parity-check-matrix generation unit 112 changes the criteria for theprevious row extraction and generates a parity check matrix includingrows different from those of the previously generated parity checkmatrix.

The determination unit 113 determines whether or not the rank of theparity check matrix generated by the parity-check-matrix generation unit112 agrees with that of the original parity check matrix. Where it isdetermined that the ranks agree with each other, the determination unit113 transmits the reception word and the generated parity check matrixto the LDPC decoding unit 121. Where it is determined that the ranks donot agree with each other, the determination unit 113 switches theprocessing back to the parity-check-matrix generation unit 112, so thatthe parity-check-matrix generation unit 112 generates another new paritycheck matrix.

As has been described, the low-density processing unit 110 reduces thedensity of the parity check matrix of the BCH code included in thereception word and transmits the low-density parity check matrix and thereception word to the LDPC decoding unit 121.

The LDPC decoding unit 112 decodes the reception words according to asum product algorithm by using the obtained low-density parity checkmatrix and externally outputs the decoded reception word outside thedecoder 100.

As described above, the low-density processing unit 110 reduces thedensity of the parity check matrix of the reception words, whereby theLDPC decoding unit 121 can perform decoding using the sum productalgorithm by using the low-density parity check matrix. Subsequently,high-performance decoding can be performed. Further, since thelow-density processing unit 110 reduces the density of the parity checkmatrix of the reception word through linear combination, the LDPCdecoding unit 121 can perform decoding on a subfield and reducing theoperation cost. That is to say, since the density of the parity checkmatrix is reduced through the linear combination before performing thedecoding using the sum product algorithm, the decoder 100 can easilyperform high-performance decoding.

Next, decoding performed by the above-described decoder will bedescribed with reference to a flowchart shown in FIG. 13.

First, the low-density processing unit 110 of the decoder 100 performsparity-check-matrix low-density processing, at step S21, so as to reducethe density of a parity check matrix included in an obtained receptionword. The details of the parity-check-matrix low-density processing willbe described later with reference to a flowchart of FIG. 14.

Then, at step S22, the LDPC decoding unit 121 performs decoding usingthe sum product algorithm (SPA) by using the parity check matrix whosedensity is reduced through the processing at step S21. Where theprocessing at the step S22 is finished, the LDPC decoding unit 121terminates decoding for the reception word. Further, the decoder 100performs the above-described decoding for each reception word (eachblock).

Next, the details of the parity-check-matrix low-density processingperformed at step S21 shown in FIG. 13 will be described with referenceto the flowchart of FIG. 14.

First, at step S41, the linear-combination calculation unit 111 of thelow-density processing unit 110 linearly combines the rows of the paritycheck matrix included in the obtained reception word in all possibleways and calculates the combination result.

After calculating the linear combination, the linear-combinationcalculation unit 111 sets the value of a variable n functioning as thecriteria of row extraction, as will be described later, to an initialvalue such as “1”, at step S42. Then, the linear-combination calculationunit 111 transmits the reception word, the linear-combinationcalculation result, and the variable n to the parity-check-matrixgeneration unit 112, so that the processing advances to step S43.

At step S43, the parity-check-matrix generation unit 112 calculatesweight indicating the number of elements whose values are determined tobe “1” for each of the obtained linear-combination results, extractsrows with predetermined weight from among all the linear-combinationresults, where the extracted weight indicating the number of elementswhose values are determined to be “1” is less than the variable n, andgenerates a low-density parity check matrix including the extractedrows.

That is to say, the parity-check-matrix generation unit 112 extracts asubset of vectors with lower weights, where the subset forms a codecomplementary space, from among the set of vectors obtained through thelinear combination calculated by the linear-combination calculation unit111, and generates a new parity check matrix including all the vectorsof the vector subset, where the vectors function as row elements.

After generating the new parity check matrix, the parity-check-matrixgeneration unit 112 advances the processing to step S44, adds “1” to thevalue of variable n, and transmits the reception word, the generatedparity check matrix, and the variable n to the determination unit 113.

Upon receiving the reception word, the generated parity check matrix,and the variable n, the determination unit 113 determines whether or notthe rank of the original parity check matrix agrees with the rank of thelow-density parity check matrix based on information relating to theoriginal parity check matrix included in the reception word, at stepS45.

For example, where it is determined that the rank of the low-densityparity check matrix is low and does not agree with that of the originalparity check matrix, the determination unit 113 returns to step S43 andrepeats the processing from then on. That is to say, the determinationunit 113 transmits its determination result to the parity-check-matrixgeneration unit 112 and makes the parity-check-matrix generation unit112 regenerate a low-density parity check matrix. At that time, thevalue of variable n functioning as the criteria of extraction from thelinear-combination result is different from that of the previousprocessing. Therefore, the parity-check-matrix generation unit 112 cangenerate a low-density parity check matrix having rows different fromthose of the previous processing (elements different from those of theprevious processing).

Where it is determined that the rank of the original parity check matrixagrees with that of the low-density parity check matrix, at step S45,the determination unit 113 advances to step S46, transmits the receptionwords and the generated low-density parity check matrix to the LDPCdecoding unit 121, and returns to step S22 shown in FIG. 13.

By performing the decoding and the parity-check-matrix low-densityprocessing in the above-described manner, the decoder 100 reduces thedensity of the parity check matrix through linear combination beforeperforming the decoding using the sum product algorithm. Therefore, thedecoder 100 can easily perform high-performance decoding.

Next, example density reduction using the above-described decoder 100will be described in detail.

In the following example, a finite field is determined to be a finitefield GF(2⁴) whose elements are powers of prime numbers (an extensionfield of degree 4 of GF(2)), a linear code is indicated by C, and a (15,7)-BCH code whose code length and data length are determined to befifteen and seven is decoded.

A parity check matrix H of the linear code C is provided, as shown inFIG. 15, for example. The parity check matrix H shown in FIG. 15 is amatrix including eight rows and fifteen columns. A Tanner graphcorresponding to the parity check matrix H is provided, as shown in FIG.16. In the Tanner graph shown in FIG. 16, each column of the paritycheck matrix H is shown as a variable node indicated by “=” and each rowis shown as a check node indicated by “+”. The density of edgesconnecting the variable nodes to the check nodes is high, which showsthat the parity check matrix H shown in FIG. 15 is not a low-densitymatrix.

As described above, the low-density processing unit 110 shown in FIG. 12performs linear combination by using the above-described eight rows andgenerates 2⁸=256 pieces of row vectors whose “1“-density is low. Then,the low-density processing unit 110 extracts fifteen pieces of rowvectors, where the number of “1” is four or less, and generates a newmatrix H_(sp4) including vertically-aligned fifteen-element vectors, asshown in FIG. 17. FIG. 18 shows a Tanner graph corresponding to thematrix H_(sp4) shown in FIG. 17. Since both the row number and thecolumn number of matrix H_(sp4) shown in FIG. 17 are fifteen, both thevariable-node number and check-node number of the Tanner graph shown inFIG. 18 are fifteen. That is to say, the density of edges connecting thevariable nodes to the check nodes is lower than in the case of FIG. 16.

The low-density processing unit 110 determines the above-describedmatrix H_(sp4) to be a parity check matrix and transmits the matrixH_(sp4) to the LDPC decoding unit 121. The LDPC decoding unit 121decodes the reception word by using the sum product algorithm by usingthe low-density parity check matrix H_(sp4) shown in FIG. 17.

FIG. 19 is a graph showing a comparison between the case where the BCHcode including the above-described parity check matrix is decoded in amaximum-likelihood manner through Viterbi decoding and the case wherethe BCH code is decoded by using the sum product algorithm by using thelow-density parity check matrix H_(sp4) shown in FIG. 17.

In FIG. 19, a curve 131 shows the bit-error rate (BER) of the decodingresult by using the sum product algorithm (SPA) ((2) bch 15 7(wgt4) SPABER) and a curve 132 indicates the bit-error rate (BER) of the decodingresult obtained by Viterbi decoding ((1) bch 15 7 ML BER). Further, dataplotted by a point 133 indicates a frame-error rate (FER) of the resultof decoding by using the sum product algorithm ((2) bch 15 7(wgt4) SPAFER) and data plotted by a point 134 indicates a frame-error rate (FER)of the decoding result obtained by Viterbi decoding ((1) bch 15 7 MLFER).

The maximum-likelihood decoding (the curve 132 shown in FIG. 19)indicates the performance limit obtained in the case where probabilitydecoding such as the sum product algorithm is used. The curve 131 usingthe present invention indicates performance growing closer to theperformance limit, as shown in FIG. 19.

As described above, the decoder 100 reduces the density of the paritycheck matrix through linear combination before decoding the BCH code byusing the sum product algorithm. Subsequently, the decoder 100 caneasily perform high-performance decoding.

Although the BCH-code decoding has been described, any code method maybe used without being limited thereto, as long as a widely-used linearcode such as a Reed-Solomon code is used. The case where theReed-Solomon signal is decoded by using the sum product algorithm willnow be described, as below.

FIG. 20 is a block diagram showing the configuration of another exampledecoder using the present invention.

In FIG. 20, a decoder 150 is a decoder compliant to the Reed-Solomoncode, for example, and includes an expansion unit 161 for expanding theparity check matrix of a reception word, a low-density processing unit170 for converting the expanded parity check matrix into a matrix whosedensity is sufficiently low, and an LDPC decoding unit 181 for decodingthe reception word using the low-density parity check matrix.

The expansion processing unit 161 expands each of the elements of aparity check matrix included in an obtained reception word to apredetermined degree according to the degree of a finite field of thematrix, as preprocessing of low-density processing for the parity checkmatrix. That is to say, the expansion processing unit 161 expands theparity check matrix on the finite field whose elements are powers ofprime numbers on a subfield of the finite field in predetermineddegrees. The low-density processing unit 161 transmits the expandedparity check matrix and the reception word to the low-density processingunit 170.

The low-density processing 170 includes a linear-combination calculationunit 171 for calculating linear combination of rows of the parity checkmatrix, a parity-check-matrix generation unit 172 for generating asufficiently sparse parity check matrix by using the linearly combinedrows, and a determination unit 173 for determining whether or not therank of the generated parity check matrix is the same as that of theoriginal parity check matrix. Since the configuration and operations ofeach of the above-described units are the same as those of thelow-density processing unit 110 of the decoder 100 shown in FIG. 12, thedescription thereof is omitted. That is to say, the units including thelinear-combination calculation unit 171 to the determination unit 173 ofthe low-density processing unit 170 correspond to those including thelinear-combination calculation unit 111 to the determination limit 113shown in FIG. 12. However, the low-density processing unit 170 performslow-density processing for the expanded parity check matrix transmittedfrom the expansion unit 161.

The low-density processing unit 170 reduces the density of the paritycheck matrix of the Reed-Solomon code expanded by the expansionprocessing unit 161 and transmits the low-density parity check matrixand the reception word to the LDPC decoding unit 181.

The LDPC decoding unit 181 decodes the reception word through the sumproduct algorithm by using the obtained low-density parity check matrixand outputs the decoded reception word outside the decoder 150.

Thus, since the expansion processing unit 161 expands the parity checkmatrix before the low-density processing unit 170 reduces the density ofthe parity check matrix, the operation cost of decoding performed by theLDPC decoding unit 181 through the sum product algorithm by using thelow-density parity check matrix H_(sp24) is reduced to about one quarterthe operation cost in the case where decoding is performed through thesum product algorithm by using the parity check matrix H included in thereception word, as shown in Equation (8) that follow.{SPA ON H_(sp24)}˜¼{SPA ON H}   Equation (8)

Subsequently, the decoder 150 can easily perform high-performancedecoding.

Next, the decoding performed by the above-described decoder 150 will bedescribed with reference to a flowchart shown in FIG. 21.

First, the expansion processing unit 161 of the decoder 150 expands aparity check matrix included in an obtained reception word according tothe degree of the finite field thereof, at step S61. Then, the expansionprocessing unit 161 transmits the expanded parity check matrix and thereception word to the low-density processing unit 170, so that theprocessing advances to step S62.

The low-density processing unit 170 performs the parity-check-matrixlow-density processing, at step S62, so that the density of the expandedparity check matrix is reduced. Since the details of theparity-check-matrix low-density processing are the same as thosedescribed with reference to the flowchart shown in FIG. 14, the detaileddescription is omitted. However, in the above-describedparity-check-matrix low-density processing, the low-density processingunit 170 reduces the density of the parity check matrix expanded by theexpansion processing unit 161 in the above-described manner.

Then, at step S63, the LDPC decoding unit 181 performs decoding throughthe sum product algorithm (SPA) by using the parity check matrix whosedensity is reduced through the processing performed, at step S62. Afterthe processing at the step S63 is finished, the LDPC decoding unit 121terminates decoding for the reception word. The decoder 150 performs theabove-described decoding for each reception word (each block).

By performing the decoding in the above-described manner, the decoder150 expands each element of the parity check matrix before performingthe density reduction. Subsequently, the decoder 150 can easily performhigh-performance decoding.

Next, example expansion performed through the above-described decoder150 will be described in detail.

In the following example, a finite field is determined to be GF(2⁴), alinear code is indicated by C, and a (15, 11)-Reed Solomon code whosecode length is determined to be fifteen and data length is determined tobe eleven is decoded. Further, the primitive root of GF(2⁴) isdetermined to be a, a primitive polynomial including the primitive roota is provided, as Equation (9), and a code-generation polynomial isprovided, as Equation (10).α⁴+α+1=0   Equation (9)g(x): =(x+1) (x+α) (x+α ²) (x+α ³)   Equation (10)

A parity check matrix of the linear code C at that time is provided, asshown in FIG. 22. The parity check matrix H shown in FIG. 22 is a matrixincluding four rows and fifteen columns. Since the finite field GF(2⁴)is an extension field of degree 4 of GF(2), all the elements and columnson the finite field GF(2⁴) can be expanded in degree four. The expansionprocessing unit 161 of the decoder 150 expands and converts the paritycheck matrix H shown in FIG. 22 into a parity check matrix H_(exp)having sixteen rows and sixty columns, as shown in FIG. 23. In thatcase, the expansion processing unit 161 expands each element of theparity check matrix H shown in FIG. 22 into a 4-by 4-element group,whereby the parity check matrix H_(exp) shown in FIG. 23 is generated.

The low-density processing unit 170 of the decoder 150 performs densityreduction for the expanded parity check matrix H_(exp). The LDPCdecoding unit 181 performs decoding through the sum product algorithm byusing the low-density parity check matrix H_(exp).

FIG. 24 is a graph showing a comparison between decoding performanceobtained where a Reed-Solomon code including the above-described paritycheck matrix is decoded through ordinary decoding and that obtainedwhere the Reed-Solomon code is decoded through the sum product algorithmby using the parity check matrix H_(sp24) obtained by reducing thedensity of the expanded parity check matrix H_(exp) shown in FIG. 23.

In FIG. 24, a curve 191 shows a bit-error rate (BER) of the result ofdecoding performed through the sum product algorithm (SPA) by using thelow-density parity check matrix H_(sp24) ((4) RS wgt24 SPA BER) and acurve 192 indicates a bit-error rate (BER) of the result of ordinarydecoding ((3) RS ORD BER). Further, data plotted by a point 193indicates a frame-error rate (FER) of the result of decoding performedthrough the sum product algorithm by using the low-density parity checkmatrix H_(sp24) ((4) RS wgt24 SPA FER) and data plotted by a point 194indicates a frame-error rate (FER) of the result of ordinary decoding((3) RS ORD FER).

The curve 191 (the point 193) denoting the result of decoding using thepresent invention shows performance higher than that of the curve 192(the point 194) denoting the result of ordinary decoding, as shown inFIG. 24.

As has been described, the decoder 150 reduces the density of the paritycheck matrix through linear combination before decoding the Reed-Solomoncode by using the sum product algorithm. Therefore, the decoder 150 caneasily achieve high-performance decoding. Further, the decoder 150expands each of the elements and columns of the parity check matrixbefore reducing the density of the parity check matrix. Subsequently,the operation cost can be reduced.

FIG. 25 is a block diagram showing the configuration of an example errorcorrection system using a Reed-Solomon code. The error correction systemshown in FIG. 25 is a system used for a digital-communication systemsuch as a digital TV, for example.

In the error correction system shown in FIG. 25, digital datatransmitted from an encoder 210 on the transmission side is transmittedto a decoder 230 on the reception side via a communication path 221 suchas the Internet, for example.

The encoder 210 includes a Reed-Solomon encoding unit 211 for encodingexternally transmitted digital data for transmission by using theReed-Solomon code, an interleaver 212 for rearranging the encodeddigital data, a convolution encoding unit 213 for performingconvolutional encoding, and a communication unit 214 for communicatingwith the decoder 230 via the communication path 221.

The Reed-Solomon encoding unit 211 encodes the digital data transmittedfrom outside the encoder 210 by using the Reed-Solomon code andtransmits the encoded digital data to the interleaver 212. Theinterleaver 212 rearranges the encoded digital data (interleaving) fordiffusing burst errors that occur mainly in the communication path 221.Since the Reed-Solomon code performs error correction, where a pluralityof bits is rearranged, as a single symbol, the interleaver 212 performssymbol interleaving for diffusing burst errors in symbols. Afterfinishing the data rearranging, the interleaver 212 transmits therearranged digital data to the convolutional-encoding unit 213.

The convolutional-encoding unit 213 refers to data that was encoded inthe past for the rearranged digital data and performs convolutionalencoding based on a plurality of data blocks, whereby a code sequence isset in order. For example, upon receiving the digital data for eachk-bit data block from the interleaver 212, the convolutional-encodingunit 213 with a constraint length K encodes the digital data to an n-bitcode block based on not only the data block transmitted at that time butalso K data blocks including data blocks that had been provided. Afterthe convolutional encoding is finished, the convolutional-encoding unit213 transmits the convolutional-encoded digital data to thecommunication unit 214.

The communication unit 214 performs communication control processing andtransmits the transmitted digital data to the decoder 230, as atransmission word via the communication path 221 based on apredetermined protocol.

The digital data transmitted from the encoder 210 is transmitted to thedecoder 230 via the communication path 221.

The decoder 230 includes a communication unit 231 for receiving thedigital data transmitted via the communication path 221, as a receptionword, a convolutional-decoding unit 232 for performing convolutionaldecoding for the reception word obtained by the communication unit 231,a deinterleaver 233 for rearranging the convolutional-decoded receptionword to its original order, and a Reed-Solomon SPA decoding unit 234 fordecoding the digital data rearranged to the original order through thesum product algorithm and reconstituting the digital data in theprevious state where Reed-Solomon encoding is not yet performed.

The communication unit 231 communicates with the communication unit 214of the encoder 210 via the communication path 221 and obtains thedigital data transmitted from the communication unit 214, as a receptionword, based on a predetermined protocol. The communication unit 231transmits the obtained reception word to the convolutional-decoding unit232.

The convolutional-decoding unit 232 decodes the reception wordtransmitted from the transmission unit 231 according to a methodcorresponding to the method of encoding performed by theconvolutional-encoding unit 213 of the encoder 210. That is to say, theconvolutional-decoding unit 232 performs soft-decision decoding for thereception word by using the BCJR (Bahl, Cocke, Jelinek, and Raviv)algorithm, the SOVA (soft output Viterbi algorithm), and so forth, forachieving Maximum a posteriori probability decoding (MAP decoding, forexample). Then, the convolutional-decoding unit 232 transmits thesoft-decision-decoded reception word to the deinterleaver 233.

The deinterleaver 233 performs data rearranging for the transmittedreception word according to a method corresponding to the interleavingperformed by the interleaver 212 of the encoder 210, performs processingfor resetting the rearranged data to the original order(deinterleaving), and transmits the reception word rearranged to theoriginal order to the Reed-Solomon SPA decoding unit 234.

Basically, the Reed-Solomon SPA decoding unit 234 is configured andoperates as is the case with the decoder 150 shown in FIG. 20. Further,the block diagram shown in FIG. 20 and the flowchart shown in FIG. 21can be used for the Reed-Solomon SPA decoding unit 234. Therefore, thedescription thereof will be omitted.

The Reed-Solomon SPA decoding unit 234 expands the parity check matrixof the reception word subjected to Reed-Solomon encoding and reduces thedensity of the parity check matrix thereof. Then, the Reed-Solomon SPAdecoding unit 234 performs decoding through the sum product algorithm byusing the parity check matrix and reconstitutes the digital data in theprevious state where encoding is not yet performed. The Reed-Solomon SPAdecoding unit 234 transmits the decoded digital data outside the decoder230.

As described above, the error correction system shown in FIG. 25 caneasily perform high-performance decoding and communications moreaccurately than ever. Further, since the decoder 230 expands eachelement and column of the parity check matrix before reducing thedensity of the parity check matrix, the operation cost for decoding canbe reduced.

Further, in the above-described embodiment, the error correction systemis used for decoding the Reed-Solomon code. However, the errorcorrection system may decode BCH codes, for example, without beinglimited to the above-described embodiment.

FIG. 26 is a block diagram showing the configuration of another exampleerror correction system using a Reed-Solomon code according to thepresent invention. The error correction system shown in FIG. 26 is asystem used for the digital-communication system such as the digital TV,for example. The same parts as those shown in FIG. 25 are designated bythe same reference numerals and the description thereof will be omitted.

In the error correction system shown in FIG. 26, digital data encoded bythe encoder 210 on the transmission side is transmitted to a decoder 240on the reception side via the communication path 221 such as theInternet, for example.

The decoder 240 includes a communication unit 241 for receiving thedigital data transmitted via the communication path 221, as a receptionword, a convolutional-decoding unit 242 for performing convolutionaldecoding for the reception word obtained by the communication unit 241,a deinterleaver 243 for rearranging the convolutional-decoded receptionword to the original order, a Reed-Solomon SPA decoding unit 244 forperforming decoding through the sum product algorithm for the digitaldata reset to the original order, so as to reconstitute the digital datain the previous state where Reed-Solomon encoding is not yet performed,and an interleaver 245 for rearranging the digital data, as is the casewith the interleaver 212 of the encoder 210.

As is the case with the communication unit 231 shown in FIG. 25, thecommunication unit 241 communicates with the communication unit 214 ofthe encoder 210 via the communication path 221 and obtains the digitaldata transmitted from the communication unit 214, as a reception word,based on a predetermined protocol. The communication unit 241 transmitsthe obtained reception word to the convolutional-decoding unit 242.

The convolutional-decoding unit 242 decodes the reception wordtransmitted from the transmission unit 241 according to a methodcorresponding to the method of encoding performed by theconvolutional-encoding unit 213 of the encoder 210. That is to say, theconvolutional-decoding unit 242 performs soft-decision decoding for thereception word by using the BCJR algorithm, the SOVA, and so forth.Then, the convolutional-decoding unit 242 transmits thesoft-decision-decoded reception word to the deinterleaver 243. Further,the reception word that had been subjected to decoding through the sumproduct algorithm is rearranged again and transmitted from theinterleaver 256 to the convolutional-decoding unit 242. Theconvolutional-decoding unit 242 performs soft-decision decoding for thereception word by using the BCJR algorithm, SOVA, and so forth, as isthe case with the reception word transmitted from the communication unit241, and transmits the reception word to the deinterleaver 243.

As is the case with the deinterleaver 233 shown in FIG. 25, thedeinterleaver 243 performs data rearranging for the reception wordtransmitted from the convolutional-decoding unit 242 according to amethod corresponding to the interleaving performed by the interleaver212 of the encoder 210, performs processing for resetting the rearrangeddata to the original order (deinterleaving), and transmits the receptionword rearranged to the original order to the Reed-Solomon SPA decodingunit 244. Further, as described above, the reception word transmittedfrom the convolutional-decoding unit 242 includes a reception wordtransmitted from the interleaver 245 via the convolutional-decoding unit242 other than the reception word transmitted from the communicationunit 241 via the convolutional-decoding unit 242.

Basically, the Reed-Solomon SPA decoding unit 244 is configured andoperates as is the case with the decoder 150 shown in FIG. 20, as in thecase of the Reed-Solomon SPA decoding unit 244 shown in FIG. 25. Theblock diagram shown in FIG. 20 and the flowchart shown in FIG. 21 can beused for the Reed-Solomon SPA decoding unit 244, as in the case of thedecoder 150.

The Reed-Solomon SPA decoding unit 244 expands the parity check matrixin the reception word obtained from the deinterleaver 243 and reducesthe density of the parity check matrix. Then, the Reed-Solomon SPAdecoding unit 244 performs decoding through the sum product algorithm byusing the parity check matrix and reconstitutes the digital data in theprevious state where encoding is not yet performed. The Reed-Solomon SPAdecoding unit 244 transmits the decoded digital data outside the decoder240. Further, the Reed-Solomon SPA decoding unit 244 transmits thedecoded digital data to the interleaver 245.

The interleaver 245 rearranges the obtained the digital data to apredetermined order, as in the case of the interleaver 212 of theencoder 210. The pattern of rearrangement performed by the interleaver245 is the same as in the case of the interleaver 212. The digital datarearranged in the above-described manner is transmitted to theconvolutional-decoding unit 242.

As has been described, the decoder 240 performs soft-decision decodingby the convolutional-decoding unit 242 and decoding through the sumproduct algorithm by the Reed-Solomon SPA decoding unit 244 for thereception word obtained by the communication unit 241 repetitively viathe deinterleaver 243 and the interleaver 245, so as to decrease theprobability of decoding errors that occur during the decoding. Thenumber of repetitions of decoding may be predetermined in advance.Otherwise, it may be determined whether or not the repetitions should bediscontinued according to a predetermined condition such as the numberof positions where error correction is performed, for example.

As described above, the decoder 240 can easily perform high-performancedecoding and the error correction system shown in FIG. 26 can performcommunications more accurately than ever. Further, since the decoder 240expands each element and column of the parity check matrix beforereducing the density of the parity check matrix, the operation cost fordecoding can be reduced.

As described above, the Reed-Solomon SPA decoding unit 244 outputs thedecoded digital data outside the decoder 240 and transmits the decodeddigital data to the interleaver 245. However, without being limited tothe above-described configuration, the Reed-Solomon SPA decoding unit244 may transmit the decoded digital data only to the interleaver 245during decoding is repetitively performed. Where the repetitions ofdecoding are terminated, the output destination of the digital data maybe switched from the interleaver 245 outside the decoder 240, so thatthe decoded digital data is output.

As described above, the error correction system is configured to decodea Reed-Solomon code. However, without being limited to theabove-described configuration, the error correction system may decode aBCH code, for example.

FIG. 27 is a block diagram illustrating the configuration of an examplerecording-and-reproducing apparatus using the error correction systemfor performing error correction by using the Reed-Solomon code accordingto the present invention. The recording-and-reproducing apparatus shownin FIG. 27 is a digital-recording-medium recording-and-reproducingapparatus, such as a DVD record player or the like.

The recording-and-reproducing apparatus 250 shown in FIG. 27 encodes theexternally transmitted digital data through the encode-processing unit260 and records the digital data onto a recording medium 272 in arecording-and-reproducing unit 270. Further, therecording-and-reproducing apparatus 250 reproduces the digital datarecorded on the recording medium 272 in the recording-and-reproducingunit 270, obtains the original digital data by performing decoding in adecode-processing unit 280, and externally outputs the data.

The encode-processing unit 260 includes first to n-th Reed-Solomonencoding units 261-1 to 261-n for performing Reed-Solomon encoding forthe digital data, where the Reed-Solomon encoding relates to degreesthat are different from one another.

The digital data transmitted from outside the encode-processing unit 260is subjected to Reed-Solomon encoding relating to degree one in thefirst Reed-Solomon encoding unit 261-1. Then, the digital data issequentially subjected to Reed-Solomon encoding relating to each ofdegrees two to n in the second to n-th Reed-Solomon encoding units 261-2to 261-n. Where the n-th Reed-Solomon encoding unit 261-n finishesencoding, the encode-processing unit 260 transmits the encoded digitaldata to the recording-and-reproducing unit 270.

The recording-and-reproducing unit 270 includes a recording unit 271 forrecording the data transmitted from the encode-processing unit 260 ontothe recording medium 272, the recording medium 272 such as an opticaldisk, for example, and a reproducing unit 273 for reproducing the datarecorded on the recording medium 272.

The recording unit 271 of the recording-and-reproducing unit 270performs NRZI (Non Return to Zero Invert) conversion (NRZI encoding) forthe digital data transmitted from the encoding unit, for example, andrecords the digital data onto the recording medium 272. Further, thereproducing unit 273 of the recording-and-reproducing unit 270reproduces the digital data recorded on the recording medium 272 (thedigital data subjected to Reed-Solomon encoding), restores (decodes) theNRZI-converted digital data, and transmits the digital data to adecode-processing unit 280.

The decode-processing unit 280 is a decoder corresponding to theencode-processing unit 260 and includes first to n-th Reed-Solomon SPAdecoding units 281-1 to 281-n for performing decoding for the digitaldata through the sum product algorithm relating to degrees that aredifferent to one another.

The first to n-th Reed-Solomon SPA decoding units 281 to 281-ncorrespond to the first to n-th Reed-Solomon encoding units 261-1 to261-n of the encode-processing unit 260, respectively, and performdecoding through the sum product algorithm-for Reed-Solomon codesrelating to the degrees. Basically, each of from the first to n-thReed-Solomon SPA decoding units 281-1 to 281-n is configured andoperates as is the case with the decoder 150 shown in FIG. 20.Subsequently, as is the case with the decoder 150, the block diagramshown in FIG. 20 and the flowchart shown in FIG. 21 can be used for thefirst to n-th Reed-Solomon SPA decoding units 281-1 to 281-n.

The decode-processing unit 280 expands each of the elements and columnsof a parity check matrix of the digital data transmitted from thereproducing unit 273 in each of from the first to n-th Reed-Solomon SPAdecoding units 281-1 to 281-n, reduces the density of the parity checkmatrix, and performs decoding relating to each degree through the sumproduct algorithm. At that time, the decode-processing unit 280 performsdecoding that is the reverse of decoding performed by theencode-processing unit 260, as shown in FIG. 27. First, thedecode-processing unit 280 performs decoding relating to the n-th degreethrough the sum product algorithm in the n-th Reed-Solomon SPA decodingunit 281-n, and subsequently performs decoding through the sum productalgorithm in decreasing order of degrees, that is, from degree n-1 todegree n-2 in the Reed-Solomon SAP decoding units that are connected inseries to one another. Finally, the decode-processing unit 280 performsdecoding through the sum product algorithm relating to degree one in thefirst Reed-Solomon SPA decoding unit 281-1. The decode-processing unit280 outputs the original digital data reconstituted in theabove-described manner outside the recording-and-reproducing apparatus250.

As described above, the decode-processing unit 280 can easily performhigh-performance decoding and the recording-and-reproducing apparatus250 can record and reproduce digital data more accurately than ever.Further, since the decode-processing unit 280 expands each of theelements and columns of the parity check matrix before reducing thedensity of the parity check matrix, the operation cost for decoding canbe reduced.

As described above, the recording-and-reproducing apparatus 250 isconfigured to decode a Reed-Solomon code. However, without being limitedto the above-described configuration, the recording-and-reproducingapparatus 250 may be configured to decode a BCH code, for example.

The above-described embodiment illustrates the recording-and-reproducingapparatus for recording and reproducing digital data. However, therecording function of recording the digital data onto the recordingmedium and the reproducing function of reproducing the digital datarecorded on the recording medium of the recording-and-reproducingapparatus 250 may be provided in units separated from each other.

FIG. 28 is a block diagram showing the configuration of an examplerecording apparatus having the same recording function as that of therecording-and-reproducing apparatus 250 shown in FIG. 27. The same partsas those shown in FIG. 27 are designated by the same reference numeralsand the description thereof is omitted.

A recording apparatus 300 shown in FIG. 28 includes theencode-processing unit 260 including the first to n-th Reed-Solomonencoders 261-1 to 261-n and a record processing unit 310 including therecording unit 271 and the recording medium 272. First, digital datatransmitted from outside the encode-processing unit 260 of the recordingapparatus 300 is subjected to Reed-Solomon encoding relating to degreeone in the first Reed-Solomon encoding unit 261-1. Next, the digitaldata subjected to the encoding relating to degree one is transmitted tothe second to n-th Reed-Solomon encoding units 261-2 to 261-n insequence and subjected to Reed-Solomon encoding relating to degrees twoto n in the units. Where the n-th Reed-Solomon encoding unit 261-nfinishes encoding, the encode-processing unit 260 transmits the encodeddigital data to the record processing unit 310.

The record processing unit 310 includes the recording unit 271 forrecording the data transmitted from the encode processing unit 260 ontothe recording medium 272 and the recording medium 272 such as an opticaldisk, for example. The recording unit 271 of the record-processing unit310 performs NRZI conversion (NRZI encoding) for the digital datatransmitted from the encode-processing unit 260, for example, andrecords the digital data onto the recording medium 272.

That is to say, as is the case with the recording-and-reproducingapparatus 250 shown in FIG. 27, the recording apparatus 300 performsReed-Solomon encoding for the digital data in the encode-processing unit260 and records the Reed-Solomon-encoded digital data onto the recordingmedium 272 under the control of the recording unit 271 of the recordprocessing unit 310.

FIG. 29 shows a recording apparatus corresponding to the above-describedrecording apparatus 300. The same parts as those shown in FIG. 27 aredesignated by the same reference numerals and the description thereof isomitted.

A reproducing apparatus 350 shown in FIG. 29 is a reproducing apparatuscorresponding to the recording apparatus 300 shown in FIG. 28 andincludes the decode-processing unit 280 including the first to n-thReed-Solomon SPA decoding units 281-1 to 281-n and a decode-processingunit 350 including the recording medium 272 and the reproducing unit273. The reproducing unit 273 of the reproducing apparatus 350reproduces the digital data recorded on the recording medium 272 (thedigital data subjected to Reed-Solomon encoding), restores (decodes) theNRZI-converted digital data, and transmits the digital data to thedecode-processing unit 280.

In the first to n-th Reed-Solomon SPA decoding units 281-1 to 281-n, thedecode-processing unit 280 expands each of the elements and columns of aparity check matrix of the digital data transmitted from the reproducingunit 273, reduces the density of the parity check matrix, and performsdecoding through the sum product algorithm relating to each degree. Atthat time, the decode-processing unit 280 performs decoding that is thereverse of decoding performed by the encode-processing unit 260, asshown in FIG. 29. First, the decode-processing unit 280 performsdecoding through the sum product algorithm relating to the n-th degreein the n-th Reed-Solomon SPA decoding unit 281-n, and subsequentlyperforms decoding through the sum product algorithm in decreasing orderof degrees, that is, from degree n-1 to degree n-2 in the Reed-SolomonSAP decoding units that are connected in series to one another. Finally,the decode-processing unit 280 performs decoding through the sum productalgorithm relating to the first degree in the first Reed-Solomon SPAdecoding unit 281-1. The decode-processing unit 280 transmits theoriginal digital data reconstituted in the above-described manneroutside the reproducing apparatus 350.

As described above, the decode-processing unit 280 can easily performhigh-performance decoding and the reproducing apparatus 350 canreproduce digital data more accurately than ever. Further, since thedecode-processing unit 280 expands each of the elements and columns ofthe parity check matrix before reducing the density of the parity checkmatrix, the operation cost for decoding can be reduced.

As described above, the recording-and-reproducing apparatus 300 isconfigured to decode a Reed-Solomon code. However, without being limitedto the above-described configuration, the recording-and-reproducingapparatus 300 may be configured to decode a BCH code, for example.

FIG. 30 is a block diagram illustrating the configuration of an examplerecording-and-reproducing apparatus using the error correction systemfor performing error correction by using Reed-Solomon codes according tothe present invention. A recording-and-reproducing apparatus 400 shownin FIG. 30 is a digital-recording-medium recording-and-reproducingapparatus, such as a DVD record player or the like, for example. Thesame parts as those shown in FIG. 27 are designated by the samereference numerals and the description thereof is omitted.

The recording-and-reproducing apparatus 400 shown in FIG. 30 encodes theexternally transmitted digital data through the encode-processing unit260 and records the digital data onto the recording medium 272 in therecording-and-reproducing unit 270. Further, therecording-and-reproducing apparatus 400 reproduces the digital datarecorded onto the recording medium 272 in the recording-and-reproducingunit 270, obtains the original digital data by performing decoding in adecode-processing unit 410, and externally outputs the data.

The decode-processing unit 410 is a decoder corresponding to theencode-processing unit 260 and includes m decoding units connected inseries, that is, first to m-th decoding units 420-1 to 420-m. Each ofthe units is configured and performs decoding as is the case with thatof the decode-processing unit 280 shown in FIG. 27.

As is the case with the decode-processing 280 shown in FIG. 27, thefirst decoding unit 420-1 includes n decoding units connected in series,that is, first to n-th Reed-Solomon SPA decoding units 421-1-1 to421-1-n that correspond to the first to n-th Reed-Solomon encoding units261-1 to 261-n of the encode-processing unit 260 and that performsdecoding through the sum product algorithm for Reed-Solomon codesrelating to the degrees. Basically, each of the first to n-thReed-Solomon SPA decoding units 421-1-1 to 421-1-n is configured andoperates, as is the case with the decoder 150 shown in FIG. 20.Therefore, the block diagram shown in FIG. 20 and the flowchart shown inFIG. 21 can be used for each of the first to n-th Reed-Solomon SPAdecoding units 421-1-1 to 421-1-n, as is the case with the decoder 150.

Each of second to m-th decoding units 420-2 to 420-m is configured andoperates as is the case with the first decoding unit 420-1. For example,the second decoding unit 420-2 includes n decoding units connected inseries, that is, first to n-th Reed-Solomon SPA decoding units 421-2-1to 421-2-n and the m-th decoding unit 420-m includes n-decoding unitsconnected in series, that is, first to n-th Reed-Solomon SPA decodingunits 421-m-1 to 421-m-n. Further, all the first to n-th Reed-SolomonSPA decoding units forming the above-described second to m-th decodingunits 420-2 to 420-m have basically the same configurations and operatein the same manner, as is the case with the decoder 150 shown in FIG.20. Therefore, the block diagram shown in FIG. 20 and the flowchartshown in FIG. 21 can be used for each of the first to n-th Reed-SolomonSPA decoding units, as is the case with the decoder 150.

First, the decode-processing unit 410 expands each of the elements andcolumns of a parity check matrix of the digital data transmitted fromthe reproducing unit 273, reduces the density of the parity checkmatrix, and performs decoding through the sum product algorithm relatingto each degree in the first to n-th Reed-Solomon SPA decoding units421-1-1 to 421-1-n of the first decoding unit 420-1.

At that time, the first decoding unit 420-1 performs decoding that isthe reverse of decoding performed by the encode-processing unit 260.First, the first decoding unit 420-1 performs decoding through the sumproduct algorithm relating to the n-th degree in the n-th Reed-SolomonSPA decoding unit 421-1-n, and subsequently performs decoding throughthe sum product algorithm in decreasing order of dimensions, that is,from degree n-1 to degree n-2 in the Reed-Solomon SPA decoding unitsthat are connected in series. Finally, the first decoding unit 420-1performs decoding through the sum product algorithm relating to thefirst degree in the first Reed-Solomon SPA decoding unit 421-1-1.

Where the decoding is finished, the first decoding unit 420-1 transmitsthe decoded digital data to the second decoding unit 420-2. The seconddecoding unit 420-2 performs decoding through the sum product algorithmin decreasing order of degrees on a one-by-one basis by using the firstto n-th Reed-Solomon SPA decoding units 421-2-1 to 421-2-n, as is thecase with the first decoding unit 420-1; and transmits the decodeddigital data to the next decoding unit. Thus, decoding is sequentiallyperformed to the m-th decoding unit 420-m. Where decoding is finished inthe m-th decoding unit 420-m, the decode-processing unit 410 outputs thedecoded digital data outside the recording-and-reproducing apparatus400.

According to the above-described configuration, the decode-processingunit 410 can easily perform high-performance decoding and therecording-and-reproducing apparatus 400 can record and reproduce digitaldata more accurately than ever. Further, since the decode-processingunit 410 expands each of the elements and columns of the parity checkmatrix before reducing the density of the parity check matrix, theoperation cost for decoding can be reduced.

In the above-described configuration, the recording-and-reproducingapparatus 400 is configured to decode a Reed-Solomon code. However,without being limited to the above-described configuration, therecording-and-reproducing apparatus 400 may be configured to decode aBCH code, for example.

The above-described embodiment illustrates the recording-and-reproducingapparatus for recording and reproducing digital data. However, therecording function of recording the digital data onto the recordingmedium and the reproducing function of reproducing the digital datarecorded on the recording medium of the recording-and-reproducingapparatus 400 may be provided in units separated from each other. Inthat case, a recording device having the same recording function as thatof the recording-and-reproducing apparatus 400 shown in FIG. 30 isconfigured and operates, as is the case with the recording apparatus 300shown in FIG. 28. Therefore, the block diagram of FIG. 28 can be usedtherefor and the description thereof is omitted.

FIG. 31 shows a reproducing device corresponding to the recordingapparatus 300, which is the recording apparatus having the samerecording function as that of the recording-and-reproducing apparatus400 shown in FIG. 30. The same parts as those shown in FIG. 30 aredesignated by the same reference numerals and the description thereof isomitted.

A reproducing device 450 shown in FIG. 31 is the reproducing devicecorresponding to the recording apparatus 300 shown in FIG. 28 and hasthe decode-processing unit 410 including the first to m-th decodingunits 420-1 to 420-m and a reproduce-processing unit 460 including therecording medium 272 and the reproducing unit 273. Further, thereproducing unit 273 of the reproducing device 450 reproduces thedigital data recorded on the recording medium 272 (the digital datasubjected to Reed-Solomon encoding), restores (decodes) theNRZI-converted digital data, and transmits the digital data to thedecode-processing unit 410.

First, the decode-processing unit 410 expands each of the elements andcolumns of the parity check matrix of the digital data transmitted fromthe reproducing unit 273, reduces the density of the parity checkmatrix, and performs decoding through the sum product algorithm for eachdegree in the first decoding unit 420-1. Subsequently, thedecode-processing unit 410 transmits the digital data to the seconddecoding units 420-2 to 420-m connected in series in sequence andperforms decoding through the sum product algorithm in the units. Wheredecoding by the m-th decoding unit 420-m is finished, thedecode-processing unit 410 outputs the decoded digital data outside therecording-and-reproducing apparatus 400.

According to the above-described configuration, the decode-processingunit 410 can easily perform high-performance decoding and thereproducing device 450 can reproduce digital data more accurately thanever. Further, since the decode-processing unit 410 expands each of theelements and columns of the parity check matrix before reducing thedensity of the parity check matrix, the operation cost for decoding canbe reduced.

In the above-described configurations, the present invention is used fordecoding a BCH code or a Reed-Solomon code. However, the presentinvention can be used for decoding any code without being limited to theabove-described configurations, so long as the code is a widely usedlinear code.

In the above-described configurations, the reproducing device 450 isconfigured to decode a Reed-Solomon code. However, without being limitedto the above-described configurations, the reproducing apparatus 400 maybe configured to decode a BCH code, for example.

Further, according to the above-described configurations, for example,the decoders and the decoding units using the present invention, such asthe decoder 100 shown in FIG. 12, the decoder 150 shown in FIG. 20, theReed-Solomon SPA decoding unit 234 shown in FIG. 25, the Reed-SolomonSPA decoding unit 244 shown in FIG. 26, the first to n-th Reed-SolomonSPA decoding units 281-1 to 281-n shown in FIG. 27, and the first tom-th decoding units 420-1 to 420-m shown in FIG. 30 reduce the densityof a parity check matrix and decode a linear code by using thelow-density check matrix, as a method for decoding an ordinary linearcode. However, without being limited to the above-described method, itmay be arranged that the density of the check matrix is reduced inadvance in other devices or other processing units, for example. In thatcase, the decoding device (or the decoding unit) decodes the linear codetransmitted from the encoder or the like by using the check matrix withthe reduced density. That is to say, the density of a check matrix isreduced in advance outside the decoder 230 shown in FIG. 25, the decoder240 shown in FIG. 26, the recording-and-reproducing apparatus 250 shownin FIG. 27, the reproducing apparatus 350 shown in FIG. 29, therecording-and-reproducing apparatus 400 shown in FIG. 30, and thereproducing device 450 shown in FIG. 31, for example. Further, each unitmay decode a transmitted linear code by using the check matrix with thereduced density.

The above-described series of processing procedures can be performed byeither hardware or software. Where the procedures are performed by thesoftware, the above-described image processing apparatus is formed as apersonal computer shown in FIG. 32, for example.

In FIG. 32, a CPU (Central Processing Unit) 501 of a personal computer500 performs various types of processing according to a program storedin the ROM (Read Only Memory) 502, or a program loaded from a storageunit 513 onto a RAM (Random Access Memory) 503. The RAM 503 furtherstores data necessary for the CPU 501 to perform the various types ofprocessing, as required.

The CPU 501, the ROM 502, and the RAM 503 are connected to one anothervia a bus 504. An input-and-output interface 510 is also connected tothe bus 504.

An input unit 511 including a keyboard, a mouse, and so forth, a displayincluding a CRT (Cathode Ray Tube), an LCD (Liquid Crystal display), orthe like, an output unit 512 including a speaker or the like, a storageunit 513 including a hard disk or the like, and a communication unit 514including a modem or the like are connected to the input-and-outputinterface 510. The communication unit 514 performs communications vianetworks including the Internet.

Further, a drive 515 is connected to the input-and-output interface 510,if necessary, and a removable medium 921 including a magnetic disk, anoptical disk, a magneto-optical disk, a semiconductor memory, and soforth, are mounted thereon, as required, and a computer program readtherefrom is installed on the storage unit 513, as required.

Where the series of processing procedures are performed through thesoftware, a predetermined program forming the software is installedthereon via a predetermined network or recording medium.

The recording medium is distributed for providing the program to a user,separate from the system, and formed not only by the removable medium521 storing the program, such as the magnetic disk (including a floppydisk), the optical disk (including a CD-ROM (Compact Disk-Read OnlyMemory) and a DVD (Digital Versatile Disk)), the magneto-optical disk(including an MD (Mini-Disk)), the semiconductor memory, and so forth,as shown FIG. 32, but also by the ROM 502 storing the program, the harddisk included in the storage unit 513, and so forth, that are mounted inthe apparatus in advance and provided to the user.

Further, in this specification, the steps describing the program storedin the recording medium include not only processing procedures performedon the time-series basis in the above-described order, but alsoprocessing procedures that are not necessarily performed on thetime-series basis but can be performed on the parallel or individualbasis.

Further, in this specification, the word system denotes the entireapparatus including the plurality of units.

INDUSTRIAL APPLICABILITY

As has been described, the present invention allows decoding an ordinarylinear code. Particularly, where a sum product algorithm is used, as amethod for decoding the ordinary linear code, high-performance decodingcan be easily performed.

1. A method for decoding a linear code on ring R, the method beingcharacterized by including: a low-density processing step for reducingthe density of elements whose values are determined to be one, for acheck matrix of the linear code; and a decoding step for decoding thelinear code through a sum product algorithm by using the check matrixwhose density is reduced through the low-density processing step.
 2. Thedecoding method according to claim 1, characterized in that the ring isa finite field including powers of prime numbers, as elements.
 3. Thedecoding method according to claim 2, characterized in that the linearcode includes a BCH code, or a Reed-Solomon code on the finite field. 4.The decoding method according to claim 1, characterized in that thelow-density processing step includes: a linear-combination calculationstep for calculating linear combination of rows of the check matrix; anda check-matrix generation step for extracting a subset of lower-weightvectors for forming a complementary space from among a vector setobtained by the linear combination calculated through thelinear-combination calculation step and generating a new check matrixincluding all the vectors of the vector subset, as row elements.
 5. Thedecoding method according to claim 4, characterized in that thelow-density processing step further includes: an expansion step forexpanding the check matrix on the finite field on a predeterminedsubfield of the finite field in a predetermined degree, wherein thelinear-combination calculation step is provided for calculating linearcombination of the rows of the check matrix expanded through theexpansion step.
 6. A decoder for a linear code on ring R, the decoderbeing characterized by including: low-density processing means thatperforms low-density processing for reducing the density of elementswhose values are determined to be one, for a check matrix of the linearcode; and decoding means for decoding the linear code through a sumproduct algorithm by using the check matrix whose density is reduced bythe low-density processing means.
 7. The decoder according to claim 6,characterized in that the ring is a finite field including powers ofprime numbers, as elements.
 8. The decoder according to claim 7,characterized in that the linear code includes a BCH code, or aReed-Solomon code on the finite field.
 9. The decoder according to claim6, characterized in that the low-density processing means includes:linear-combination calculation means for calculating linear combinationof rows of the check matrix; and check-matrix generation means forextracting a subset of lower-weight vectors for forming a complementaryspace from among a vector set obtained by the linear combinationcalculated by the linear-combination calculation means and generating anew check matrix including all the vectors of the vector subset, as rowelements.
 10. The decoder according to claim 9, characterized in thatthe low-density processing means further includes expansion means forexpanding the check matrix on the finite field on a predeterminedsubfield of the finite field in a predetermined degree, wherein thelinear-combination calculation means calculates linear combination ofrows of the check matrix expanded through the expansion means.
 11. Thedecoder according to claim 6, characterized by further includingsoft-decision decoding means for performing soft-decision decoding for alinear code subjected to convolutional encoding, wherein the low-densityprocessing means reduces the density of the elements whose values aredetermined to be one, for the check matrix of the linear code subjectedto the soft-decision decoding by the soft-decision decoding means. 12.The decoder according to claim 11, characterized in that thesoft-decision decoding by the soft-decision decoding means, thelow-density processing by the low-density processing means, and thedecoding by the decoding means are repetitively performed. 13.(canceled)
 14. A method for decoding a linear code on ring R, thedecoding method being characterized by including: an input step forinputting a reception value; and a decoding step for decoding the linearcode through a sum product algorithm, for a check matrix of the linearcode, by using the check matrix, where the density of elements whosevalues are determined to be one is reduced, and the reception valueinput through the input step.
 15. A decoder for a linear code on ring R,the decoder being characterized by including: input means for inputtinga reception value; and decoding means for decoding the linear codethrough a sum product algorithm, for a check matrix of the linear code,by using the check matrix, where the density of elements whose valuesare determined to be one is reduced, and the reception value input bythe input means.
 16. A program for making a computer decode a linearcode on ring R, characterized in that the computer is made to performprocessing including: an input step for inputting a reception value; anda decoding step for decoding the linear code through a sum productalgorithm, for a check matrix of the linear code, by using the checkmatrix, where the density of elements whose values are determined to beone is reduced, and the reception value input through the input step.17-32. (canceled)